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<title>DM-CtrlH7-BF-DevProgram: C:/Users/ASUS/Desktop/dm-ctrlH7-balance-9025test/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h File Reference</title>
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<div class="header">
  <div class="headertitle"><div class="title">stm32h7xx_hal_uart_ex.h File Reference</div></div>
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<p>Header file of UART HAL Extended module.  
<a href="#details">More...</a></p>
<div class="textblock"><code>#include &quot;<a class="el" href="stm32h7xx__hal__def_8h_source.html">stm32h7xx_hal_def.h</a>&quot;</code><br />
</div>
<p><a href="stm32h7xx__hal__uart__ex_8h_source.html">Go to the source code of this file.</a></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 id="header-nested-classes" class="groupheader"><a id="nested-classes" name="nested-classes"></a>
Classes</h2></td></tr>
<tr class="memitem:UART_5FWakeUpTypeDef" id="r_UART_5FWakeUpTypeDef"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_u_a_r_t___wake_up_type_def.html">UART_WakeUpTypeDef</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">UART wake up from stop mode parameters.  <a href="struct_u_a_r_t___wake_up_type_def.html#details">More...</a><br /></td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 id="header-define-members" class="groupheader"><a id="define-members" name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:gadaec9a23646032a333a5327d66aae4fe" id="r_gadaec9a23646032a333a5327d66aae4fe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___u_a_r_t_ex___word___length.html#gadaec9a23646032a333a5327d66aae4fe">UART_WORDLENGTH_7B</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gae19a4c9577dfb1569cf6f564fe6c4949">USART_CR1_M1</a></td></tr>
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<tr class="memitem:gaf867be43de35fd3c32fe0b4dd4058f7e" id="r_gaf867be43de35fd3c32fe0b4dd4058f7e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___u_a_r_t_ex___word___length.html#gaf867be43de35fd3c32fe0b4dd4058f7e">UART_WORDLENGTH_9B</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gaaf15ab248c1ff14e344bf95a494c3ad8">USART_CR1_M0</a></td></tr>
<tr class="memitem:ga6599292020c484faeea894307d9dc6d5" id="r_ga6599292020c484faeea894307d9dc6d5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___u_a_r_t_ex___wake_up___address___length.html#ga6599292020c484faeea894307d9dc6d5">UART_ADDRESS_DETECT_4B</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memitem:ga4dbd5995e0e4998cb1a312c183d7cbb0" id="r_ga4dbd5995e0e4998cb1a312c183d7cbb0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___u_a_r_t_ex___wake_up___address___length.html#ga4dbd5995e0e4998cb1a312c183d7cbb0">UART_ADDRESS_DETECT_7B</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga2d8588feb26d8b36054a060d6b691823">USART_CR2_ADDM7</a></td></tr>
<tr class="memitem:gaf55427ab3ae02f380954508d80b6dea3" id="r_gaf55427ab3ae02f380954508d80b6dea3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___u_a_r_t_ex___f_i_f_o__mode.html#gaf55427ab3ae02f380954508d80b6dea3">UART_FIFOMODE_DISABLE</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memitem:ga3ff44f476a9c4d0e6c98e50f513f3561" id="r_ga3ff44f476a9c4d0e6c98e50f513f3561"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___u_a_r_t_ex___f_i_f_o__mode.html#ga3ff44f476a9c4d0e6c98e50f513f3561">UART_FIFOMODE_ENABLE</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gafb5e9fc4111b0159c65811f6a206c192">USART_CR1_FIFOEN</a></td></tr>
<tr class="memitem:gac0167b844b8cc2d183b55a0b296b2803" id="r_gac0167b844b8cc2d183b55a0b296b2803"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___u_a_r_t_ex___t_x_f_i_f_o__threshold__level.html#gac0167b844b8cc2d183b55a0b296b2803">UART_TXFIFO_THRESHOLD_1_8</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memitem:ga7b6a3451b4d3677ba49f05228832edad" id="r_ga7b6a3451b4d3677ba49f05228832edad"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___u_a_r_t_ex___t_x_f_i_f_o__threshold__level.html#ga7b6a3451b4d3677ba49f05228832edad">UART_TXFIFO_THRESHOLD_1_4</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga3cc91bacf5659188d4ef8d13fc48b5c3">USART_CR3_TXFTCFG_0</a></td></tr>
<tr class="memitem:ga3ded7de796281c47106eab832068534d" id="r_ga3ded7de796281c47106eab832068534d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___u_a_r_t_ex___t_x_f_i_f_o__threshold__level.html#ga3ded7de796281c47106eab832068534d">UART_TXFIFO_THRESHOLD_1_2</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga4651a05997c8bef8485185f7c8874142">USART_CR3_TXFTCFG_1</a></td></tr>
<tr class="memitem:ga0dd7780c824caddd1476cb59b9d5e5d0" id="r_ga0dd7780c824caddd1476cb59b9d5e5d0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___u_a_r_t_ex___t_x_f_i_f_o__threshold__level.html#ga0dd7780c824caddd1476cb59b9d5e5d0">UART_TXFIFO_THRESHOLD_3_4</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga3cc91bacf5659188d4ef8d13fc48b5c3">USART_CR3_TXFTCFG_0</a>|<a class="el" href="group___peripheral___registers___bits___definition.html#ga4651a05997c8bef8485185f7c8874142">USART_CR3_TXFTCFG_1</a>)</td></tr>
<tr class="memitem:ga8e36c5786a037adae9a124a3094fc374" id="r_ga8e36c5786a037adae9a124a3094fc374"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___u_a_r_t_ex___t_x_f_i_f_o__threshold__level.html#ga8e36c5786a037adae9a124a3094fc374">UART_TXFIFO_THRESHOLD_7_8</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gaa2683f01784119560144bd0c7fd8d85e">USART_CR3_TXFTCFG_2</a></td></tr>
<tr class="memitem:ga302d541c0419d26567cc0da09486e73d" id="r_ga302d541c0419d26567cc0da09486e73d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___u_a_r_t_ex___t_x_f_i_f_o__threshold__level.html#ga302d541c0419d26567cc0da09486e73d">UART_TXFIFO_THRESHOLD_8_8</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gaa2683f01784119560144bd0c7fd8d85e">USART_CR3_TXFTCFG_2</a>|<a class="el" href="group___peripheral___registers___bits___definition.html#ga3cc91bacf5659188d4ef8d13fc48b5c3">USART_CR3_TXFTCFG_0</a>)</td></tr>
<tr class="memitem:ga9cabde9885fe477df3625fa8fdc7a99a" id="r_ga9cabde9885fe477df3625fa8fdc7a99a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___u_a_r_t_ex___r_x_f_i_f_o__threshold__level.html#ga9cabde9885fe477df3625fa8fdc7a99a">UART_RXFIFO_THRESHOLD_1_8</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memitem:ga46898e3dbaa13a52a62ae7dbddc90cd5" id="r_ga46898e3dbaa13a52a62ae7dbddc90cd5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___u_a_r_t_ex___r_x_f_i_f_o__threshold__level.html#ga46898e3dbaa13a52a62ae7dbddc90cd5">UART_RXFIFO_THRESHOLD_1_4</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gaf8b113e8d794dc256745b970cc2e4704">USART_CR3_RXFTCFG_0</a></td></tr>
<tr class="memitem:ga032d8a09e993ca8938eb6fa5b97f4d16" id="r_ga032d8a09e993ca8938eb6fa5b97f4d16"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___u_a_r_t_ex___r_x_f_i_f_o__threshold__level.html#ga032d8a09e993ca8938eb6fa5b97f4d16">UART_RXFIFO_THRESHOLD_1_2</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga216b1b9afd21e8e4ba132605aacf7534">USART_CR3_RXFTCFG_1</a></td></tr>
<tr class="memitem:ga822019dbcf489602fe72d84700655e27" id="r_ga822019dbcf489602fe72d84700655e27"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___u_a_r_t_ex___r_x_f_i_f_o__threshold__level.html#ga822019dbcf489602fe72d84700655e27">UART_RXFIFO_THRESHOLD_3_4</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gaf8b113e8d794dc256745b970cc2e4704">USART_CR3_RXFTCFG_0</a>|<a class="el" href="group___peripheral___registers___bits___definition.html#ga216b1b9afd21e8e4ba132605aacf7534">USART_CR3_RXFTCFG_1</a>)</td></tr>
<tr class="memitem:gaba2b8f47d6b307a644ec4dcd6d8202e4" id="r_gaba2b8f47d6b307a644ec4dcd6d8202e4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___u_a_r_t_ex___r_x_f_i_f_o__threshold__level.html#gaba2b8f47d6b307a644ec4dcd6d8202e4">UART_RXFIFO_THRESHOLD_7_8</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga24cb2175b76382753462bed1d36d518c">USART_CR3_RXFTCFG_2</a></td></tr>
<tr class="memitem:gabc5dc474eeac764ab6e99435ace5ca21" id="r_gabc5dc474eeac764ab6e99435ace5ca21"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___u_a_r_t_ex___r_x_f_i_f_o__threshold__level.html#gabc5dc474eeac764ab6e99435ace5ca21">UART_RXFIFO_THRESHOLD_8_8</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga24cb2175b76382753462bed1d36d518c">USART_CR3_RXFTCFG_2</a>|<a class="el" href="group___peripheral___registers___bits___definition.html#gaf8b113e8d794dc256745b970cc2e4704">USART_CR3_RXFTCFG_0</a>)</td></tr>
<tr class="memitem:ga2d8ffd4cb12754846ace609dff92e8df" id="r_ga2d8ffd4cb12754846ace609dff92e8df"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___u_a_r_t_ex___private___macros.html#ga2d8ffd4cb12754846ace609dff92e8df">UART_GETCLOCKSOURCE</a>(__HANDLE__,  __CLOCKSOURCE__)</td></tr>
<tr class="memdesc:ga2d8ffd4cb12754846ace609dff92e8df"><td class="mdescLeft">&#160;</td><td class="mdescRight">Report the UART clock source.  <br /></td></tr>
<tr class="memitem:gad9330184a8bd9399a36bcc93215a50d1" id="r_gad9330184a8bd9399a36bcc93215a50d1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___u_a_r_t_ex___private___macros.html#gad9330184a8bd9399a36bcc93215a50d1">UART_MASK_COMPUTATION</a>(__HANDLE__)</td></tr>
<tr class="memdesc:gad9330184a8bd9399a36bcc93215a50d1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Report the UART mask to apply to retrieve the received data according to the word length and to the parity bits activation.  <br /></td></tr>
<tr class="memitem:gaf856254e5a61d2ee81086918bffabde5" id="r_gaf856254e5a61d2ee81086918bffabde5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___u_a_r_t_ex___private___macros.html#gaf856254e5a61d2ee81086918bffabde5">IS_UART_WORD_LENGTH</a>(__LENGTH__)</td></tr>
<tr class="memdesc:gaf856254e5a61d2ee81086918bffabde5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ensure that UART frame length is valid.  <br /></td></tr>
<tr class="memitem:gaa4cf2a15ad7ae46e2905debeef35a908" id="r_gaa4cf2a15ad7ae46e2905debeef35a908"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___u_a_r_t_ex___private___macros.html#gaa4cf2a15ad7ae46e2905debeef35a908">IS_UART_ADDRESSLENGTH_DETECT</a>(__ADDRESS__)</td></tr>
<tr class="memdesc:gaa4cf2a15ad7ae46e2905debeef35a908"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ensure that UART wake-up address length is valid.  <br /></td></tr>
<tr class="memitem:ga59f192f936bea1dac321a552ab3e662d" id="r_ga59f192f936bea1dac321a552ab3e662d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___u_a_r_t_ex___private___macros.html#ga59f192f936bea1dac321a552ab3e662d">IS_UART_TXFIFO_THRESHOLD</a>(__THRESHOLD__)</td></tr>
<tr class="memdesc:ga59f192f936bea1dac321a552ab3e662d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ensure that UART TXFIFO threshold level is valid.  <br /></td></tr>
<tr class="memitem:gac6cc8376326d3982bda0685dbaaff687" id="r_gac6cc8376326d3982bda0685dbaaff687"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___u_a_r_t_ex___private___macros.html#gac6cc8376326d3982bda0685dbaaff687">IS_UART_RXFIFO_THRESHOLD</a>(__THRESHOLD__)</td></tr>
<tr class="memdesc:gac6cc8376326d3982bda0685dbaaff687"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ensure that UART RXFIFO threshold level is valid.  <br /></td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 id="header-func-members" class="groupheader"><a id="func-members" name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:ga27862dc24258939a758a877b674977af" id="r_ga27862dc24258939a758a877b674977af"><td class="memItemLeft" align="right" valign="top">
<a class="el" href="stm32h7xx__hal__def_8h.html#a63c0679d1cb8b8c684fbb0632743478f">HAL_StatusTypeDef</a>&#160;</td><td class="memItemRight" valign="bottom"><b>HAL_RS485Ex_Init</b> (<a class="el" href="group___u_a_r_t___exported___types.html#ga5de4a49eb132735325e706f406c69d6e">UART_HandleTypeDef</a> *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)</td></tr>
<tr class="memitem:ga44d09cdf66fec468d956c64a23f61856" id="r_ga44d09cdf66fec468d956c64a23f61856"><td class="memItemLeft" align="right" valign="top">
void&#160;</td><td class="memItemRight" valign="bottom"><b>HAL_UARTEx_WakeupCallback</b> (<a class="el" href="group___u_a_r_t___exported___types.html#ga5de4a49eb132735325e706f406c69d6e">UART_HandleTypeDef</a> *huart)</td></tr>
<tr class="memitem:ga9275d738be064c56277b69384e6e3d14" id="r_ga9275d738be064c56277b69384e6e3d14"><td class="memItemLeft" align="right" valign="top">
void&#160;</td><td class="memItemRight" valign="bottom"><b>HAL_UARTEx_RxFifoFullCallback</b> (<a class="el" href="group___u_a_r_t___exported___types.html#ga5de4a49eb132735325e706f406c69d6e">UART_HandleTypeDef</a> *huart)</td></tr>
<tr class="memitem:ga6136c1516c4319853fba64290aed1e9d" id="r_ga6136c1516c4319853fba64290aed1e9d"><td class="memItemLeft" align="right" valign="top">
void&#160;</td><td class="memItemRight" valign="bottom"><b>HAL_UARTEx_TxFifoEmptyCallback</b> (<a class="el" href="group___u_a_r_t___exported___types.html#ga5de4a49eb132735325e706f406c69d6e">UART_HandleTypeDef</a> *huart)</td></tr>
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<tr class="memitem:gad113d7b5cd162ca36e706d812801b5ab" id="r_gad113d7b5cd162ca36e706d812801b5ab"><td class="memItemLeft" align="right" valign="top">
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<tr class="memitem:ga5f321105c87423e7156dbab60826b37a" id="r_ga5f321105c87423e7156dbab60826b37a"><td class="memItemLeft" align="right" valign="top">
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<tr class="memitem:gae2e0da62ac7e71641ee696f6b6a3de11" id="r_gae2e0da62ac7e71641ee696f6b6a3de11"><td class="memItemLeft" align="right" valign="top">
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<tr class="memitem:gae70c60d3f42f1c205ebc834de99342a7" id="r_gae70c60d3f42f1c205ebc834de99342a7"><td class="memItemLeft" align="right" valign="top">
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<tr class="memitem:ga548dd91f3e20cb5919972465571b9c98" id="r_ga548dd91f3e20cb5919972465571b9c98"><td class="memItemLeft" align="right" valign="top">
<a class="el" href="group___u_a_r_t___exported___types.html#gadddf3d5480235c945dc8eec58f961203">HAL_UART_RxEventTypeTypeDef</a>&#160;</td><td class="memItemRight" valign="bottom"><b>HAL_UARTEx_GetRxEventType</b> (const <a class="el" href="group___u_a_r_t___exported___types.html#ga5de4a49eb132735325e706f406c69d6e">UART_HandleTypeDef</a> *huart)</td></tr>
</table>
<a name="details" id="details"></a><h2 id="header-details" class="groupheader">Detailed Description</h2>
<div class="textblock"><p>Header file of UART HAL Extended module. </p>
<dl class="section author"><dt>Author</dt><dd>MCD Application Team </dd></dl>
<dl class="section attention"><dt>Attention</dt><dd></dd></dl>
<p>Copyright (c) 2017 STMicroelectronics. All rights reserved.</p>
<p>This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS. </p>
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